1. Technical Field
The present invention relates to a CCD (Charge Coupled Device) type solid-state image capturing apparatus, a driving method thereof, and an electronic apparatus, such as a camera, provided with the solid-state image capturing apparatus.
2. Description of the Related Art
As a solid-state image capturing apparatus, a charge coupled device (CCD) type solid-state image capturing apparatus has been well known in the related art. According to the CCD type solid-state image capturing apparatus (hereinafter, referred to as a CCD solid-state image capturing apparatus), a plurality of light sensing units, each including a photoelectric conversion unit (i.e., a photodiode) for generating signal charges corresponding to the amount of received light and accumulating the signal charges, are two-dimensionally arranged in a matrix formation. Signal charges are generated based on light signals of an object, which are incident into the photodiodes of the plurality of light sensing units, and then accumulated. The signal charges are transferred in the vertical direction by a plurality of vertical transfer registers having a CCD structure, which are arranged in each column of the light sensing units, and also transferred in the horizontal direction by horizontal transfer registers having a CCD structure. Then, the signal charges transferred in the horizontal direction are output from an output unit having a charge/voltage conversion section as image information of the object. The output unit, typically, includes a floating diffusion (FD) and a source follower amplifier which is connected to end terminals of the horizontal transfer registers, that is, a floating diffusion type amplifier. In addition, the output unit may include a floating gate type amplifier.
In the CCD solid-state image capturing apparatus, a so called interline transfer (IT) scheme has been well known in the related art, which transfers charges by using an image capturing area, which includes the plurality of light sensing units arranged in a two-dimensional matrix formation and the plurality of vertical transfer registers, and the horizontal transfer registers connected to the plurality of vertical transfer registers. Further, in the CCD solid-state image capturing apparatus, a so called frame interline transfer (FIT) scheme has been well known in the related art, which transfers charges by using the image capturing area, a storage section including a plurality of vertical transfer registers, and horizontal transfer registers connected to the plurality of vertical transfer registers of the storage section.
The CCD solid-state image capturing apparatus, for example, has been extensively used for digital still cameras, digital video cameras or the like. Further, the CCD solid-state image capturing apparatus is used as a solid-state image capturing apparatus which is mounted on mobile apparatuses such as phones provided with cameras or PDAs (Personal Digital Assistants).
According to a CCD solid-state image capturing apparatus of the related art, a plurality of vertical transfer electrodes of a vertical transfer register are formed by a bi-layer polysilicon film in such a manner that vertical transfer electrodes of a first layer polysilicon film partially overlap vertical transfer electrodes of a second layer polysilicon film. Such a CCD solid-state image capturing apparatus has a structure in which all vertical transfer electrodes, including a vertical transfer electrode to which a reading voltage VT is applied, extend to channel stop regions provided in parallel to a channel region of the vertical transfer register. The vertical transfer electrode, to which the reading voltage VT is applied, serves as a so called reading electrode.
Meanwhile, as a CCD solid-state image capturing apparatus, a solid-state image capturing apparatus, in which a plurality of vertical transfer electrodes arranged in the transfer direction are formed by a single layer (i.e., an identical layer) polysilicon film, has also been used in the related art. FIGS. 13 and 14 are views illustrating one example of an existing CCD solid-state image capturing apparatus in which a plurality of vertical transfer electrodes are formed by a single layer polysilicon film. FIG. 13 is a plan view illustrating main elements of an image capturing region and FIG. 14 is a sectional view taken along line XIV-XIV of FIG. 13. In FIGS. 13 and 14, only the main elements are shown while other elements are omitted, for example, a light blocking layer, a color filter, an on chip lens or the like which are all above the transfer electrodes.
As shown in FIG. 13, in the CCD solid-state image capturing apparatus 100, photodiodes (PDs) serving as light sensing units 101 having a rectangular shape are two-dimensionally arranged in a matrix formation, and vertical transfer registers 102 having a CCD structure are disposed corresponding to columns of the light sensing units 101. The vertical transfer registers 102 read signal charges from the light sensing units 101, and then transfer the signal charges in the vertical direction. Each vertical transfer register 102 includes an embedded transfer channel region 103, and the plurality of vertical transfer electrodes formed above the transfer channel region 103 while interposing a gate insulating layer therebetween. In the example, three vertical transfer electrodes correspond to the photodiode (PD) serving as one light sensing unit 101, that is, the plurality of vertical transfer electrodes 104 to 106 are formed by a single layer, that is, a first layer polysilicon film. Vertical transfer electrodes are held in common in both the upper and lower vertical transfer electrodes 104 and 106 and upper and lower unit pixels thereof.
The vertical transfer electrodes 104 and 106 are continuously formed in the horizontal direction through between the light sensing units 101, which are adjacent to each other in the vertical direction, such that electrodes corresponding to the vertical transfer registers 102 are connected to each other. Meanwhile, among the three vertical transfer electrodes 104 to 106, the central vertical transfer electrode 105 serves as a reading electrode. Since the vertical transfer electrode 105 serving as the reading electrode is independently formed in an island shape, the vertical transfer electrode 105 is connected through a connection interconnection 107 formed by a second layer polysilicon film. The connection interconnection 107 includes a band-shaped section 107B disposed on the vertical transfer electrodes 104 and 106, which extend between the light sensing units 101 adjacent to each other in the vertical direction, while interposing an insulating layer therebetween, and an extension section 107A extending above the vertical transfer electrode 105 while being integrally formed with the band-shaped section 107B. The extension section 107A is connected to a contact section 108 of the vertical transfer electrode 105 in each vertical transfer register 102.
The embedded transfer channel region 103 is formed in a linear shape in the vertical direction. In order to be provided in parallel to the embedded transfer channel region 103 while making contact with the embedded transfer channel region 103, a first channel stop region 111 for separating pixels adjacent to each other in the horizontal direction is formed in a linear shape between the pixels adjacent to each other in the horizontal direction. Further, a second channel stop region 112 for separating pixels adjacent to each other in the vertical direction is formed between the pixels adjacent to each other in the vertical direction. The second channel stop region 112 includes a horizontal region between the pixels adjacent to each other in the vertical direction, and a region which vertically extends toward the light sensing unit 101 while partially making contact with the embedded transfer channel region 103. The first and second channel stop regions 111 and 112 are formed by a semiconductor region which contains impurities, for example, a p type semiconductor region.
The vertical transfer electrodes 104 to 106 are formed over the first and second channel stop regions 111 and 112.
When viewed in the sectional view, as shown in FIG. 14, a second conductive type (e.g., a p type) first semiconductor well region 116 is formed on a first conductive type (e.g., an n type) semiconductor substrate 115, and the photodiode (PD) serving as the light sensing unit 101 is formed in the p type first semiconductor well region 116. The photodiode (PD) includes an n type semiconductor region 117 and a p+ type semiconductor region 118 that controls dark current. The p type first semiconductor well region 116 includes the n type embedded transfer channel region 103, the first p+ channel stop region 111, and the second p+ channel stop region 112 (not shown). A p type second semiconductor well region 119 is formed immediately below the embedded transfer channel region 103.
The respective corresponding vertical transfer electrodes 104 to 106 are formed above the embedded transfer channel region 103, a charge reading gate section 121 and the first p+ channel stop region 111 while interposing a gate insulating layer (e.g., a silicon oxide layer 122). In FIG. 13, the vertical transfer electrode 105 serving as the reading electrode is formed.
In the above-described CCD solid-state image capturing apparatus in which the vertical transfer electrodes are formed by the bi-layer polysilicon film, the configuration, in which all the vertical transfer electrodes extend onto the channel stop region, is due to the following reasons. The first reason is to ensure a design margin resulting from a mask alignment error of the channel region of the vertical transfer register and the vertical transfer electrode.
Further, as shown in FIG. 15, vertical transfer electrodes 131 and 133 formed by a first layer polysilicon film and a vertical transfer electrode 132 formed by a second layer polysilicon film are arranged in the transfer direction while overlapping each other. A recess 134 of a pattern at the overlapped part of the vertical transfer electrodes 131 to 133 may easily occur in the second layer polysilicon film which is the vertical transfer electrode 132 to which a reading voltage VT is applied. The recess 134 occurs because the thickness or width of a resist pattern serving as a mask in the vicinity of a stepped portion is not uniform in a photolithography process due to the influence of the stepped portion at the overlapped part, and an electrode width varies somewhat when viewed in a plan view. The second reason is to prevent exposure of a channel region 135 due to the recess pattern by setting the electrode width to be thick. When the vertical transfer electrode 132 formed by the second layer polysilicon film is drawn by a line overlapping the channel region 135, a part of the underlying channel region 135 is exposed by the recess 134. In a state in which the vertical transfer electrode is not relatively largely covered by the channel region 135, the potential at the portion becomes deeper, so that a problem may occur in charge transfer.
When a pixel cell is not fine, a gate insulating layer is formed to have a certain thickness, and an impurity concentration of a channel stop region is not high, even if the vertical transfer electrode, to which the reading voltage VT is applied, is formed to extend onto the channel stop region, a problem may not significantly be obvious. This corresponds to another reason.
Meanwhile, even in a CCD solid-state image capturing apparatus in which the plurality of vertical transfer electrodes as shown in FIGS. 13 and 14 are formed by a single layer polysilicon film, the plurality of vertical transfer electrodes extend onto the channel stop region 111 by reasons similar to the above-described reasons. That is, in the related art, the necessity of removing the overlapping of the channel stop regions 111 and 112 and the vertical transfer electrodes 104 to 106 is not recognized. That is, even if the channel stop regions 111 and 112 overlap the vertical transfer electrodes 104 to 106, a problem may not be obvious.
As prior literatures, Japanese Patent No. 3885769, Japanese Unexamined Patent Application Publication No. 9-266296 and Japanese Unexamined Patent Application Publication No. 2004-228328 are described. Japanese Patent No. 3885769 discloses a configuration in which the width of a vertical transfer electrode is substantially identical to the width of a transfer channel region. With such a configuration, as compared with an existing solid-state image capturing apparatus, a region (i.e., a canopy section in light blocking) of a portion, which does not exist on the vertical transfer electrode, is widened during the light blocking, and smear characteristics varying depending on the length of a canopy section can be improved.
Japanese Unexamined Patent Application Publication No. 9-266296 discloses a configuration in which, immediately below an n type embedded transfer channel of a vertical transfer register, a p type semiconductor region having a low impurity concentration is formed at the center portion thereof, and p type semiconductor regions having a high impurity concentration are formed at both sides thereof. With such a configuration, the smear is reduced, and a fringing electric field of charge transfer at the center portion of the transfer channel region is increased, so that transfer efficiency is ensured. In the sectional structure of the drawing, a vertical transfer electrode serving as a reading electrode does not extend onto a p+ element isolation layer, but there is no special implication.
Japanese Unexamined Patent Application Publication No. 2004-228328 discloses a configuration in which a vertical transfer electrode formed by a bi-layer polysilicon film is provided, and a vertical transfer electrode formed by a first layer polysilicon film is formed in a recess of a substrate surface. A part of the vertical transfer electrode formed by the first layer polysilicon film is formed over a channel stop portion. If the vertical transfer electrode is formed in the substrate recess, since an upper surface of a unit cell is planarized before the formation of the polysilicon film, which becomes the vertical transfer electrode of the second layer, a process of forming the vertical transfer electrode is simplified.
As described above, in a CCD solid-state image capturing apparatus in which a pixel size is not relatively fine, even if a vertical transfer electrode overlaps a channel stop region, no problem occurs. That is, in an existing structure in which a gate insulating layer is relatively thick and the impurity concentration of the channel stop region and embedded transfer channel region is not relatively high, so long as the reading voltage VT is not excessively increased, even if the channel stop region overlaps the vertical transfer electrode, no problems occur.